CoWoS and advanced packaging
Methods that join several chip dies, such as logic and HBM, in one package; CoWoS, from TSMC, is a key bottleneck for AI accelerators.
Advanced packaging places multiple dies, such as a compute die and HBM stacks, in one package connected by dense, short interconnects, instead of building one large monolithic chip. CoWoS (chip-on-wafer-on-substrate) is TSMC's 2.5D packaging approach, which uses a silicon interposer to link the dies. Packaging is a separate step from wafer fabrication and has its own capacity.
Traders care because packaging capacity has at times limited AI accelerator output even when wafer supply was sufficient. Outsourced assembly and test firms also handle parts of the process, so their capacity and customer mix matter. Expansions of packaging capacity are a useful signal to track alongside wafer output.
Worked example (illustrative numbers, not real data): a vendor has wafers for 10,000 compute dies per quarter but packaging capacity for only 7,000. Its accelerator output is capped at 7,000 packaged units, whatever the wafer supply.