Synopsys and TSMC announce silicon-proven IP milestones and A14 design flow work

Synopsys announced TSMC-related milestones across its IP and EDA portfolio, including the first silicon bring-up of M-PHY v6.0 IP on TSMC N2P and a 64G UCIe IP tape-out. It also said agentic run assistance for Fusion Compiler on A14 is in development with TSMC, and that Ansys tools are being enabled for co-packaged optics. The announcement shows the IP and EDA business is tied to TSMC's 2nm-class and A14 roadmap.

• M-PHY v6.0 IP: first silicon bring-up on TSMC N2P, described as an industry first
• 64G UCIe IP taped out
• 224G IP in development for co-packaged optical Ethernet and UALink
• Co-packaged optics enablement on TSMC COUPE using Ansys Zemax, Lumerical and HFSS-IC Pro